1. Field of the Invention
The present invention relates to a field-effect transistor, a manufacturing process thereof and a circuit comprising a plurality of such transistors.
2. Description of the Related Art
Over the last several years, organic and mixed transition metal oxide semiconductor channel based field-effect transistors (FETs) have been extensively studied because they can potentially lead to low-end consumer electronic applications that can be produced at a very low cost on large areas, and on flexible or free-form substrates.
Two critical aspects for the realization of these technologies relate to: 1) the environmental and electrical stability of FETs; and 2) to its low voltage operation. The most common sign of device degradation manifests itself as a threshold voltage shift upon prolonged gate bias stress. Other changes that could arise under bias stress are an increase in the sub-threshold slope, reductions of the field-effect mobility, an increase in the OFF current and/or hysteresis between subsequent measurements.
Emerging FET technologies such as those based on organic or transition metal oxide semiconductors suffer from electrical instabilities but offer some advantages over Si-based technologies in that they can be processed at lower temperatures and potentially at a lower cost. In the literature, several routes have been taken to improve the stability of FETs and can be summarized as follows: 1) passivation of gate dielectric/semiconductor interface 2) variation of gate dielectric materials; 3) annealing at high temperatures; 4) variation of source and drain metal electrodes. Among the wide variety of materials used as gate dielectric, fluoropolymers, such as CYTOP, have shown potential to produce interfaces with organic semiconductors with very low trap densities. WO03/052841 in the name of Avecia Ltd (hereby incorporated by reference in its entirety) discloses a process of manufacturing such organic field-effect transistors, where CYTOP has been used in combination with one or more further insulator layers. However, polymers have typically a very low dielectric constant. The latter in conjunction with a large thickness required to avoid large leakage currents, results in a low capacitance density. On the other hand, gate dielectrics with high capacitance can be achieved through the use of inorganic high-k dielectric materials. However, in general the performance of the known devices with a multi-layer dielectric in bias stress tests is unacceptable for many applications.
D. K. Hwang et al., “Top-Gate Organic Field-Effect Transistors with High Environmental and Operational Stability,” Adv. Mater. 23, 1293-1298 (2011); D. K. Hwang et al., “Flexible and stable solution-processed organic field-effect transistors,” Organic Electronics, 12, 1108 (2011); and D. K. Hwang et al., “Hysteresis mechanisms of pentacene thin-film transistors with polymer/oxide bilayer gate dielectrics,” Appl. Phys. Lett. 92, 013304 (2008) are hereby incorporated by reference in their entireties.